HW/SW codesign of the MPEG-2 video decoder

In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made timing power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided on hardware implementation of the IDCT and VLD algorithms. The remaining parts were realized in software with a 32-bit RISC processor. The MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in high-level Verilog/VHDL hardware description language and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on an industrial prototyping board.