Testing embedded cores by weighted sum of selected node voltages

The utilization of re-useable Intellectual Property (IP) cores for System-on-Chip (SoC) design can shorten the time-to-market and thus reduce the design cost but on the other hand, the challenge of testing such embedded IP cores is initiated. This paper presents a Built-In Self-Test (BIST) technique based on the weighted sum of selected node voltages (WSSNV) for the effective testing of these embedded cores. The proposed BIST technique can greatly reduced the number of testing I/O pins and thus reduce the size and simplify the design of test architecture for SoC. Besides, testing time and procedure are reduced and simplified respectively since only one testing output is needed to be observed.