DocumentCode :
1665219
Title :
Energy aware design methodologies for application specific NoC
Author :
Choudhary, Naveen ; Gaur, M.S. ; Laxmi, V. ; Singh, Virendra
Author_Institution :
Dept. of Comput. Eng., Malaviya Nat. Inst. of Technol., Jaipur, India
fYear :
2010
Firstpage :
1
Lastpage :
4
Abstract :
Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not necessarily conform to regular topologies. In this work, a methodology using the priori knowledge of the application´s communication characteristic for the design of customized and energy optimized irregular NoC is proposed.
Keywords :
integrated circuit design; low-power electronics; network routing; network-on-chip; application specific NoC; application specific SoC design; communication framework; communication requirements; customized NoC architectures; deadlock-free routing; energy aware design methodology; high-performance nanoscale architecture; low power consumption; network-on-chip; Biological cells; Clocks; Energy efficiency; Network topology; Routing; System-on-a-chip; Topology; Core Graph; NP-hard; NoC; Optimization; SoC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP, 2010
Conference_Location :
Tampere
Print_ISBN :
978-1-4244-8972-5
Electronic_ISBN :
978-1-4244-8971-8
Type :
conf
DOI :
10.1109/NORCHIP.2010.5669451
Filename :
5669451
Link To Document :
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