DocumentCode
1665242
Title
Single-clock, single-latch, scan design
Author
Sheth, Amit M. ; Savir, Jacob
Author_Institution
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Volume
1
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
613
Abstract
This paper describes a new scan design that uses the same clock for both scan and functional mode. A test made signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.
Keywords
CMOS logic circuits; flip-flops; logic design; logic testing; shift registers; timing; LSSD double latch design structure; functional mode; hardware overhead; high-speed scan capability; level sensitive scan design; scan design; scan mode; shift register latch; single-clock scan design; single-latch scan design; test mode signal; Circuit testing; Clocks; Design for testability; Hardware; Jacobian matrices; Latches; Logic; Master-slave; Pins; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE
ISSN
1091-5281
Print_ISBN
0-7803-7218-2
Type
conf
DOI
10.1109/IMTC.2002.1006912
Filename
1006912
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