A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS

High-data-rate short-range communication and image systems beyond 100GHz impose crucial requirements on signal sources, demanding superior purity and stability. Using frequency multipliers with high efficiency and multiplication factor to generate the N^th harmonic signal that is phase-locked by a PLL at the fundamental frequency provides an alternative solution. The desired signal in an active frequency multiplier can be generated using Class B/C amplifiers, where a half-wave signal containing all harmonics is first created and then filtered to remove the undesired harmonic components [1]. Another approach is to apply the same signal to both the IF and RF ports of a mixer to construct a doubler followed by cascading to form the quadrupler [3]. The linear superposition (LS) technique that superimposes four phase-shifted half-waves of 0°, 90°, 180°, and 270° is another popular scheme [5]. For multipliers with high multiplication factors, these prior techniques may offer very low power efficiency (η). Quadrupler cores based on Class B/C amplifiers, mixers, or the LS technique had been reported with η of 0.9% [1], 0.04% [3] and 0.0002% [5], respectively. Therefore, instead of improving the η of the multiplier cores, the design of the subsequent amplifiers after the multiplier to boost the η and output power has become a popular approach. We have substantially enhanced the η of a frequency quadrupler core using a phase-controlled push-push (PCPP) technique to directly synthesize the 4^th harmonic. We noted that in an ideal situation, the proposed quadrupler circuit is able to generate almost no other harmonics, attaining an η of 50%. In this paper, we present a 121-to-137GHz frequency quadrupler based on a 0.13μm SiGe BiCMOS process. For the purpose of measurement, a balun coupled with buffers to provide the differential signals is also designed. The DC power con- umptions of the quadrupler core and input buffers are 6.4mW and 28.8mW, respectively. Our demonstrated quadrupler core is able to achieve 9% (1.6% including input buffers) power efficiency at 1.6V, with a -2.4dBm output signal.