Modelling programmable logic devices and reconfigurable, microprocessor-related architectures

This paper introduces two basic models for describing the space efficiency and the throughput of configurable devices. The first model focuses on available programmable logic devices (PLD) and shows the relationships of silicon space and computing time to the block size. This model is further subdivided into a particular one for complex PLDs (CPLD) and one for field-programmable gate arrays (FPGA) due to the fact that both incorporate different implementations of programmable logic. The second model was developed to describe the behaviour of block-based, reconfigurable architectures like the recently introduced universal configurable block (UCB) system with respect to block sizes. All models show a specific behaviour concerning the needed silicon area and the data throughput. Consequently these models are useful to determine optimum values for block sizes in different logic architectures.