An optically differential reconfigurable gate array with a dynamic reconfiguration circuit

An optically differential reconfigurable gate array (ODRGA) using a dynamic circuit technique is proposed to reduce the area occupied by the configuration circuit on a VLSI chip. The ODRGA reconfiguration process is performed by calculating the difference between previous configuration data stored on a VLSI chip and subsequent optically-supplied configuration data. The reconfiguration circuit of our previously proposed ODRGA using static circuit techniques required a large implementation area. This paper introduces a new dynamic reconfiguration circuit and compares an estimate of its area on the VLSI chip with that obtained by the static technique.