Title :
An 1.2V 440-MS/s 0.13-µm CMOS pipelined Analog-to-Digital Converter with 5-8bit mode selection
Author :
Nieminen, Tero ; Halonen, Kari
Author_Institution :
Sch. of Sci. & Technol., Dept. of Micro- & Nanosci., Aalto Univ., Aalto, Finland
Abstract :
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83 mA.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; comparators (circuits); operational amplifiers; pipeline processing; CMOS pipelined analog-to-digital converter; comparator; current 83 mA; double-sampling; effective-number-of-bits; offset error compensation; operational amplifier; redundant sign digit; size 0.13 mum; voltage 1.2 V; word length 5 bit to 8 bit; CMOS integrated circuits; Capacitors; Clocks; Frequency measurement; Pipelines; Semiconductor device measurement; Solid state circuits;
Conference_Titel :
NORCHIP, 2010
Conference_Location :
Tampere
Print_ISBN :
978-1-4244-8972-5
Electronic_ISBN :
978-1-4244-8971-8
DOI :
10.1109/NORCHIP.2010.5669463
