A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Author

Harwood, Mike ; Nielsen, Steffen ; Szczepanek, Andre ; Allred, Richard ; Batty, Sean ; Case, Mike ; Forey, Simon ; Gopalakrishnan, Karthik ; Kan, Larry ; Killips, Bob ; Mishra, Parmanand ; Pande, Rohit ; Rategh, Hamid ; Ren, Alan ; Sanders, Jeff ; Schoy,

Author_Institution

Inphi, Northampton, UK

fYear

2012

Firstpage

326

Lastpage

327

Abstract

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.

Keywords

CMOS integrated circuits; equalisers; integrated optoelectronics; optical fibre networks; optical links; optical transceivers; 100GBASE-LR4-OTL4.4 gearbox; OIF 28G-VSR standard; analog equalization; bit rate 100 Gbit/s; bit rate 25 Gbit/s to 30 Gbit/s; generic CMOS SerDes; jitter performance; low-power transceivers; optical links; optical networking; optical sub-assemblies; optical transport lane 4.4 applications; power 225 mW; size 40 nm; CMOS integrated circuits; Clocks; Equalizers; Finite impulse response filter; Optical transmitters; Receivers; Regulators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-0376-7

Type

conf

DOI

10.1109/ISSCC.2012.6177032

Filename

6177032