• DocumentCode
    1666209
  • Title

    High-level design error diagnosis using backtrace on decision diagrams

  • Author

    Raik, Jaan ; Repinski, Urmas ; Ubar, Raimund ; Jenihhin, Maksim ; Chepurov, Anton

  • Author_Institution
    Tallinn Univ. of Technol., Tallinn, Estonia
  • fYear
    2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The paper proposes a method for locating design errors at the source-level of hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models. The method is based on backtracing the mismatched and matched outputs of the system under verification on HLDDs. Experiments on a set of sequential register-transfer level benchmarks show that the method is capable of locating the design errors injected with a high accuracy and a short run time. In fact all the errors injected in the experiments were identified as top suspects by the proposed diagnosis algorithm.
  • Keywords
    backtracking; decision diagrams; error detection; fault diagnosis; hardware description languages; high level languages; sequential circuits; backtracing; decision diagram; design error; design representation; error diagnosis; hardware description language code; high level decision diagram; sequential register transfer; Algorithm design and analysis; Benchmark testing; Circuit faults; Clocks; Design methodology; Hardware; Labeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    NORCHIP, 2010
  • Conference_Location
    Tampere
  • Print_ISBN
    978-1-4244-8972-5
  • Electronic_ISBN
    978-1-4244-8971-8
  • Type

    conf

  • DOI
    10.1109/NORCHIP.2010.5669486
  • Filename
    5669486