Title :
Unbiased guard ring for latchup-resistant, junction-isolated smart-power ICs
Author :
Gupta, Sandhya ; Beckman, J.C. ; Kosier, S.L.
Author_Institution :
PolarFab, Bloomington, MN, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
The measurements of the effects of high current, emitter area, and layout of unbiased guard rings are reported and explained. Measurements show a reduction of the parasitic gain by up to six orders of magnitude, while also avoiding the crosstalk and power consumption of biased rings
Keywords :
crosstalk; integrated circuit layout; integrated circuit measurement; isolation technology; power integrated circuits; silicon; Si; Si measurements; emitter area; high current; high-voltage PBC4 technology; junction-isolated smart-power ICs; latchup-resistant smart-power ICs; layout; parasitic gain reduction; unbiased guard rings; Area measurement; Costs; Current measurement; Energy consumption; Gain measurement; Hazards; Integrated circuit measurements; Integrated circuit reliability; Power measurement; Spontaneous emission;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, Proceedings of the 2001
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-7019-8
DOI :
10.1109/BIPOL.2001.957887
