Combined instruction and loop parallelism in array synthesis for FPGAs

Compiling perfect, uniform dependence loops to FPGA based co-processors normally yields processor (PE) arrays where a PE executes one instance of the loop body per clock cycle. We develop a transformation framework in which the derived PE can be systematically and automatically pipelined through retiming. We use well known transformations-skewing and serialization-by which an arbitrary number of registers may be placed at the PE outputs. They are then moved into the PE data-path using standard commercial circuit retimers. Our experiments (based on performance estimates after place-and-route) have been very encouraging. For a number of examples we have seen dramatic performance improvements: speed increases of an order of magnitude with relatively little (always less than 100%) area overhead.