DocumentCode :
1667261
Title :
Scheduling and partitioning for multiple loop nests
Author :
Wang, Zhong ; Zhuge, Qingfeng ; Sha, Edwin H M
Author_Institution :
Dept of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
fYear :
2001
fDate :
6/23/1905 12:00:00 AM
Firstpage :
183
Lastpage :
188
Abstract :
This paper presents the multiple loop partition scheduling technique, which combines the loop partition and prefetching. It can exploit the data locality better than the traditional loop partition, which only focus on a singleton nested loop and loop fusion. Moreover, multiple loop partition scheduling balances the computation and memory loading, such that the long memory latency can be hidden effectively. The experiments shows that multiple loop partition scheduling can achieve the significant improvement over the existed methods.
Keywords :
digital signal processing chips; hardware-software codesign; parallel architectures; processor scheduling; program control structures; storage management; DSP processing; loop fusion; memory latency; memory loading; multiple loop partition scheduling; nested loop; prefetching; program models; Costs; Delay; Digital signal processing; Image processing; Mathematics; Permission; Prefetching; Processor scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Synthesis, 2001. Proceedings. The 14th International Symposium on
Print_ISBN :
1-58113-418-5
Type :
conf
DOI :
10.1109/ISSS.2001.156554
Filename :
957936
Link To Document :
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