Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques

A method based on software pipelining has been previously proposed to optimize mono-phase clocked sequential circuits. The resulting circuits are multi-phase clocked sequential circuits, where all clocks have the same period. To preserve functionality of the original circuit, registers must be placed according to a correct schedule. This schedule also ensures the maximum throughput. In that method, it is question of (1) how to determine a schedule that requires the minimum number of registers, and (2) how to place these registers optimally. In this paper, problems (1) and (2) are tackled simultaneously. More precisely, we deal with the problem of determining schedules with the minimum register requirements, where the optimal register placement is done during the schedule determination. To optimally solve that problem, we provide a mixed integer linear program that we use to derive a linear program, which is polynomial-time solvable. We show that the dual of this linear program can be transformed to a minimum cost network flow problem, which can be solved more efficiently. Experimental results confirm the effectiveness of the approach, and show that significant reductions of the number of registers can be obtained. Also, they confirm that the obtained dual formulation can be solved much faster than its primal.