Title :
Dynamic configuration using pyramidal architecture FPGA and a built-in RISC processer
Author :
Sawan, M. ; Rabel, C.E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
fDate :
6/20/1905 12:00:00 AM
Abstract :
This paper presents a new pyramidal architecture FPGA (PARC) including a RISC processor dedicated for fast dynamic configurations systems. The PARC FPGA consists of a large number of fine-grained array of optimized heterogenous logic blocks and a new pyramidal structure with three hierarchical levels. The proposed FPGA is a reprogrammable SRAM based device. The built-in processor is designed as a 16-bit microprocessor with a reduced instruction set (32 instructions), hardware and software interrupts, and 16-bit address and data buses. The whole device has been developed with Synopsys design automation CAD tools, using VHDE and the 0.8 μm BiCMOS technology from Nortel to operate at a 50 MHz clock frequency
Keywords :
BiCMOS digital integrated circuits; field programmable gate arrays; microprocessor chips; reduced instruction set computing; 0.8 micron; 16 bit; 50 MHz; BiCMOS technology; built-in RISC processer; dynamic configuration; pyramidal architecture FPGA; Design automation; Embedded software; Field programmable gate arrays; Hardware; Logic arrays; Logic devices; Microprocessors; Process design; Random access memory; Reduced instruction set computing;
Conference_Titel :
Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on
Conference_Location :
Monastir
Print_ISBN :
0-7803-4969-5
DOI :
10.1109/ICM.1998.825557
