Title :
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology
Author :
Lee, Daeyeal ; Chang, Ik Joon ; Yoon, Sang-Yong ; Jang, Joonsuc ; Jang, Dong-Su ; Hahn, Wook-Ghee ; Park, Jong-Yeol ; Kim, Doo-Gon ; Yoon, Chiweon ; Lim, Bong-Soon ; Min, Byung-Jun ; Yun, Sung-Won ; Lee, Ji-Sang ; Park, Il-Han ; Kim, Kyung-Ryun ; Yun, Jeo
Author_Institution :
Samsung Electron., Hwasung, South Korea
Abstract :
The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].
Keywords :
NAND circuits; flash memories; DDR interface MLC NAND flash; P3-pattern prepulse scheme; bit rate 533 Mbit/s; correction-before-coupling reprogram; fast throughput; floating-gate coupling interference; inhibit-channel-coupling-reduction technique; memory size 64 GByte; mobile applications; multilevel cell NAND flash memory; program disturbance; size 20 nm; smart phones; sub-20nm technology node; tablet computers; wave-pipeline architecture; Bit error rate; Computer architecture; Flash memory; Interference; Microprocessors; Pipelines; Timing;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6177077
