FPGA implemented fast two´s complement serial-parallel multiplier with PCI interface

In this paper, a new design of serial-parallel multipliers based on the modified Booth algorithm is proposed. The proposed multiplier implementation on a PCI initiator/target interface card (where a single chip design, XC4010E, is used to implement a PCI local bus interface, revision 2.1, protocol and timing compliance) is demonstrated. The flexible design of the PCI-interface can be easily adapted for specific interface requirements. This interface card can be used for different DSP applications. The multiplier is compared with one proposed recently in terms of speed and hardware, and is shown to be faster (for large multipliers, it tends to provide double speed), and having a lower area x time² complexity. An implementation using a FPGA-based PCI-interface card has been made for an 8×8 multiplier. The design was tested using simulation software