DocumentCode
166765
Title
Automated latchup analysis
Author
Vashchenko, V.A. ; Shibkov, A.A.
fYear
2014
fDate
7-12 Sept. 2014
Firstpage
1
Lastpage
8
Abstract
A new simulation approach to the analysis of the low voltage latchup in CMOS process and the high voltage latchup in BCD process technologies is presented. The approach uses new automated numerical algorithm simulating real standard three-stage latchup test and relies on parameterized 2-D mixed-mode simulation of a finite-element model (FEM) structure that represents the parasitic structure formed in the physical IC layout.
Keywords
BIMOS integrated circuits; CMOS integrated circuits; electronic design automation; integrated circuit layout; 2D mixed-mode simulation; BCD process; CMOS process; automated latchup analysis; automated numerical algorithm; finite element model; high voltage latchup; low voltage latchup; physical IC layout; CMOS process; Integrated circuit modeling; Layout; Power supplies; Semiconductor device modeling; Thyristors; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
Conference_Location
Tucson, AZ
ISSN
0739-5159
Type
conf
Filename
6968818
Link To Document