DocumentCode
1667665
Title
Synthesis of low power circuits using combined pass logic and CMOS topologies
Author
Gallant, Michael ; Al-Khalili, Dhamin
Author_Institution
Apple Comput. Inc., Cupertino, CA, USA
fYear
1998
fDate
6/20/1905 12:00:00 AM
Firstpage
59
Lastpage
62
Abstract
This paper describes the development of a logic synthesis tool designed specifically to work with a reduced set cell library based primarily on pass logic circuit cells in combination with standard CMOS gates. Circuits synthesized with this tool were compared to circuits synthesized by Synopsys´ Design Analyzer using a standard CMOS cell library, for the same benchmarks. An average of 43% improvement in power-delay product has been achieved
Keywords
CMOS logic circuits; circuit CAD; integrated circuit design; logic CAD; low-power electronics; BDDMAP mapping algorithm; combined pass logic/CMOS topologies; logic synthesis tool; low power circuits; pass logic circuit cells; power-delay product improvement; reduced set cell library; standard CMOS gates; Boolean functions; CMOS logic circuits; Circuit synthesis; Circuit topology; Data structures; Libraries; Logic circuits; Multiplexing; Power dissipation; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on
Conference_Location
Monastir
Print_ISBN
0-7803-4969-5
Type
conf
DOI
10.1109/ICM.1998.825567
Filename
825567
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