Title :
CDM protection of a 3D TSV memory IC with a 100 GB/s wide I/O data bus
Author :
Nagata, M. ; Takaya, Satoshi ; Ikeda, Hinata ; Linten, D. ; Scholz, Matthias ; Chen, Shih-Hung ; Hasegawa, Kiyotomo ; Shintani, Taizo ; Sawada, Masanori
Author_Institution :
Kobe Univ., Nada, Japan
Abstract :
For the first time, CDM stress tests are studied on a 3D TSV stacked IC for memory applications. The stacked dies have each their ESD protection, but no dedicated ESD protection was placed on the TSVs. A CDM protection level of more than 1.5 kV is obtained.
Keywords :
electrostatic discharge; integrated circuit testing; storage management chips; three-dimensional integrated circuits; 3D TSV memory IC; 3D TSV stacked IC; CDM protection; CDM stress tests; ESD protection; bit rate 100 Gbit/s; stacked dies; wide I/O data bus; Electrostatic discharges; Pins; Stress; Three-dimensional displays; Through-silicon vias; Voltage measurement;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
Conference_Location :
Tucson, AZ
