DocumentCode :
166786
Title :
Threshold voltage shift due to incidental pulse on non-stressed pins during HBM testing
Author :
Yue Zu ; Liang Wang ; Sankaralingam, Rajkumar ; Ward, Scott ; Schichl, Joe
Author_Institution :
Analog ESD Team, Texas Instrum. Inc., Dallas, TX, USA
fYear :
2014
fDate :
7-12 Sept. 2014
Firstpage :
1
Lastpage :
6
Abstract :
An unexpected voltage pulse in ESD HBM tester´s non-stress channels led to phase shift error failure in a sensitive phase comparator circuit. The failure occurred due to threshold voltage shift of the input PMOS transistor. This unwarranted stress was shown to come from relay capacitance and distributed resistance of relay-based HBM tester.
Keywords :
MOSFET; electrostatic discharge; failure analysis; phase comparators; semiconductor device testing; ESD HBM tester; HBM testing; PMOS transistor; distributed resistance; incidental pulse; nonstress channels; nonstressed pins; phase comparator circuit; phase shift error failure; relay capacitance; relay-based HBM tester; threshold voltage shift; voltage pulse; Electrostatic discharges; Logic gates; Pins; Relays; Resistance; Stress; Voltage measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
Conference_Location :
Tucson, AZ
ISSN :
0739-5159
Type :
conf
Filename :
6968829
Link To Document :
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