Title :
System-level ESD failure diagnosis with chip-package-system dynamic ESD simulation
Author :
Myoung, Robert ; Byong-su Seol ; Chang, Nicolas
Author_Institution :
ANSYS, Inc., San Jose, CA, USA
Abstract :
A comprehensive chip-package-system (CPS) electrostatic discharge (ESD) simulation methodology is developed for addressing IEC61000-4-2 testing conditions. An innovative chip ESD compact model is proposed, combined with full-wave models of the ESD gun, ESD protection devices, PCB wires/vias and connectors for CPS analysis. Two examples of CPS ESD application are illustrated demonstrating good correlation with measurement.
Keywords :
chip scale packaging; electrostatic discharge; fault diagnosis; integrated circuit modelling; CPS analysis; CPS electrostatic discharge simulation methodology; ESD gun; ESD protection devices; IEC61000-4-2 testing conditions; PCB wires-vias; chip ESD compact model; chip-package-system ESD simulation methodology; connectors; full-wave models; system-level ESD failure diagnosis; Abstracts; Electrostatic discharges; Integrated circuit modeling; Power measurement; Semiconductor device measurement; Time measurement;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
Conference_Location :
Tucson, AZ
