• DocumentCode
    166792
  • Title

    System-level ESD failure diagnosis with chip-package-system dynamic ESD simulation

  • Author

    Myoung, Robert ; Byong-su Seol ; Chang, Nicolas

  • Author_Institution
    ANSYS, Inc., San Jose, CA, USA
  • fYear
    2014
  • fDate
    7-12 Sept. 2014
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    A comprehensive chip-package-system (CPS) electrostatic discharge (ESD) simulation methodology is developed for addressing IEC61000-4-2 testing conditions. An innovative chip ESD compact model is proposed, combined with full-wave models of the ESD gun, ESD protection devices, PCB wires/vias and connectors for CPS analysis. Two examples of CPS ESD application are illustrated demonstrating good correlation with measurement.
  • Keywords
    chip scale packaging; electrostatic discharge; fault diagnosis; integrated circuit modelling; CPS analysis; CPS electrostatic discharge simulation methodology; ESD gun; ESD protection devices; IEC61000-4-2 testing conditions; PCB wires-vias; chip ESD compact model; chip-package-system ESD simulation methodology; connectors; full-wave models; system-level ESD failure diagnosis; Abstracts; Electrostatic discharges; Integrated circuit modeling; Power measurement; Semiconductor device measurement; Time measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
  • Conference_Location
    Tucson, AZ
  • ISSN
    0739-5159
  • Type

    conf

  • Filename
    6968832
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=166792