DocumentCode :
1668122
Title :
Metal nanocrystal memory with sol-gel derived HfO2 high-к tunneling oxide
Author :
Chen, Shih-Tang ; Huang, Kun-Cheng ; Chen, Hua-Chiang ; Liu, Fu-Ken ; Leu, Ching-Chich
Author_Institution :
Dept. of Chem. & Mater. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan
fYear :
2010
Firstpage :
1212
Lastpage :
1213
Abstract :
A metal-oxide-semiconductor (MOS) capacitor structure containing gold (Au) nanoparticles (NPs) within sol-gel derived HfO2 high-κ oxide is fabricated. Firstly, the Au NPs with particle size of about 3.3 nm were synthesized by chemical reduction method. Then the 10 nm-thick HfO2 tunneling oxide, the Au NPs and the 15 nm-thick HfO2 control oxide were prepared by spin coating method to construct a Si/HfO2/Au NPs/HfO2 memory structure. The sol-gel derived ultra-thin HfO2 high-κ oxide layer showed good electrical properties and were critical to desirable memory property of the MOS structure. The high-frequency capacitance-voltage(C-V) measurements demonstrated the well defined counterclockwise hysteresis memory loops which was originated from the Au nanocrystals. By utilizing high-k HfO2 as tunneling oxide, the MOS structure showed memory effect even at a low voltage of ± 2 V. The flat-band voltage shift was about 0.8 V by a swapping voltage between ±5 V. Although the memory window was not so large, the MOS showed better retention characteristics by replacing SiO2 with HfO2 as tunneling oxide. Therefore, we have successfully fabricated nanocrystal memory device with HfO2 high-κ tunneling oxide which are attractive for low operation voltage non-volatile memory applications.
Keywords :
MOS capacitors; flash memories; gold; hafnium compounds; nanofabrication; nanoparticles; random-access storage; sol-gel processing; spin coating; Au-HfO2; chemical reduction method; counterclockwise hysteresis memory loops; flat-band voltage shift; gold nanoparticles; high-κ tunneling oxide; high-frequency capacitance-voltage measurements; metal nanocrystal memory; metal-oxide-semiconductor capacitor structure; nonvolatile memory applications; size 10 nm; size 15 nm; sol-gel process; spin coating method; swapping voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanoelectronics Conference (INEC), 2010 3rd International
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-3543-2
Electronic_ISBN :
978-1-4244-3544-9
Type :
conf
DOI :
10.1109/INEC.2010.5424947
Filename :
5424947
Link To Document :
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