Title :
Synthesis support for design partitioning
Author :
Willoughby, John
Author_Institution :
Cadence Design Syst., USA
Abstract :
As designs become larger and larger it becomes necessary to partition the design, not only to meet synthesis tool restrictions, but also to perform parallel design processing by multiple engineers and/or on multiple machines. Partitioning requires the assignment of timing and loading budgets across module boundaries. This is an inefficient and time-consuming task if performed by hand. Logic synthesis tools can utilize techniques of constraint propagation combined with hierarchical controls to perform this task automatically. This approach will result in improved results and shorter design times
Keywords :
constraint handling; hardware description languages; high level synthesis; logic gates; logic partitioning; timing; constraint propagation; design partitioning; hardware description language; hierarchical controls; loading budgets; logic synthesis tools; module boundaries; multiple engineers; multiple machines; parallel design processing; synthesis support; synthesis tool; time-consuming; timing; Automatic control; Automatic logic units; Boundary conditions; Circuit synthesis; Design engineering; Logic design; Pins; Runtime; Strain control; Timing;
Conference_Titel :
Verilog HDL Conference, 1997., IEEE International
Conference_Location :
Santa Clare, CA
Print_ISBN :
0-8186-7955-7
DOI :
10.1109/IVC.1997.588529
