Author :
Hara, Takahiko ; Fukuda, Koichi ; Kanazawa, Kazuhisa ; Shibata, Noboru ; Hosono, Koji ; Maejima, Hiroshi ; Nakagawa, Michio ; Abe, Takumi ; Kojima, Masatsugu ; Fujiu, Masaki ; Takeuchi, Yoshiaki ; Amemiya, Kazumi ; Morooka, Midori ; Kamei, Teruhiko ; Nasu
Abstract :
A 146 mm2 8 Gb NANO flash memory with 4-level programmed cells is fabricated in a 70 nm CMOS technology. A single-sided pad architecture and extended block-addressing scheme without redundancy is adopted for die size reduction. The programming throughput is 6 MB/s and is comparable to binary flash memories.
Keywords :
CMOS memory circuits; flash memories; integrated circuit layout; logic design; 4-level programmed cells; 6 MB/s; 70 nm; 8 Gbit; CMOS technology; NAND flash memory; binary flash memories; die size reduction; extended block-addressing scheme; memory core layout; single-sided pad architecture; CMOS image sensors; CMOS technology; Cellular phones; Costs; Digital cameras; Driver circuits; Flash memory; Throughput; Universal Serial Bus; Videos;
