f/sub T/ variation caused by channel width effects in ladder gate structure for RF SOI MOSFETs

The scaling down of CMOS-SOI technologies have challenged the deep-submicron minimum feature size. This-promises great expectations for CMOS RF applications. The gate length along with the relative wide gate width in RF circuits leads to reconsideration of gate design. We present f/sub T/ and f/sub max/ properties associated with layout and body resistance of the ladder structure in PD-SOI devices and the resulting speed characteristics (strong function of the number of fingers and gate shape types such as T-gate and H-gate) is evaluated by g/sub m/ variation (/spl Delta/g/sub m/) and extra parasitic capacitance (/spl Delta/C/sub gs/).