Title :
A mechanism for logic upset induced by power-on ESD
Author :
Yang Xiu ; Thomson, Nicholas ; Mertens, Robert ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.
Keywords :
CMOS logic circuits; electrostatic discharge; CMOS IO; ESD protection; N+ diffusion; contact discharge; core circuitry; logic upset; parasitic NPN structure; power-on ESD; test chip; transistor sizing; Electrostatic discharges; Inverters; Latches; Logic circuits; Logic gates; Substrates; Transistors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
Conference_Location :
Tucson, AZ
