Title :
A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming
Author :
Taub, Mase ; Bains, Rupinder ; Barkley, Gerald ; Castro, Hernan ; Christensen, Gregory ; Eilert, Sean ; Fackenthal, Rich ; Giduturi, Hari ; Goldman, Matthew ; Haid, Chris ; Haque, Rezaul ; Parat, Krishna ; Peterson, Steve ; Proescholdt, Andrew ; Ramamurth
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm2 with a cell size of 0.076 μm2.
Keywords :
CMOS memory circuits; flash memories; multivalued logic circuits; 1.5 MByte/s; 166 MHz; 512 Mbit; 90 nm; configurable output buffers; dual-row programming; memory cell size; multilevel cell flash memory; negative deselected rows; program control hardware optimization; synchronous operation; triple-well CMOS technology; x-decoder; Computer buffers; Costs; Flash memory; Hardware; Lithography; Nonvolatile memory; Parallel programming; Temperature sensors; Throughput; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493865
