• DocumentCode
    1668410
  • Title

    A 126 mm2 4 Gb multilevel AG-AND flash memory with 10 MB/s programming throughput

  • Author

    Kurata, H. ; Sasago, Y. ; Otsuga, K. ; Arigane, T. ; Kawamura, T. ; Kobayashi, T. ; Kume, H. ; Homma, K. ; Kozakai, K. ; Noda, S. ; Ito, T. ; Shimizu, M. ; Ikeda, Y. ; Tsuchiya, O. ; Furusawa, K.

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • fYear
    2005
  • Firstpage
    56
  • Abstract
    A 4 Gb flash memory, fabricated in 90 nm CMOS technology, results in a 126 mm2 chip size and a 0.0162 μm2/b cell size. Address and temperature compensation methods control the resistance of the inversion-layer local bit-line. A programming throughput of 10 MB/s is achieved by using a self-boosted charge injection scheme.
  • Keywords
    CMOS memory circuits; compensation; flash memories; multivalued logic circuits; 10 MB/s; 4 Gbit; 90 nm; CMOS; address compensation; inversion-layer local bit-line resistance control; multilevel AG-AND flash memory; programming throughput; self-boosted charge injection; temperature compensation; CMOS process; Digital cameras; Flash memory; Indium tin oxide; Random access memory; Temperature control; Temperature dependence; Temperature distribution; Throughput; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493866
  • Filename
    1493866
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1668410