• DocumentCode
    1668456
  • Title

    A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization

  • Author

    Sorna, M. ; Beukerna, T. ; Selander, K. ; Zier, S. ; Ji, B. ; Murfet, P. ; Mason, J. ; Rhee, W. ; Ainspan, H. ; Parker, B.

  • Author_Institution
    IBM Corp., East Fishkill, NY, USA
  • fYear
    2005
  • Firstpage
    62
  • Abstract
    A 4.9 to 6.4 Gb/s 2-level SerDes ASIC I/O core designed in 0.13 μm CMOS uses a 4-tap FFE in the transmitter and a 5-tap DFE with receiver AGC. Error-free operation is achieved on channels with over 30 dB loss at the half-baud rate. The TXRX pair consumes 290 mW from a 1.2 V supply and uses a die area of 0.79 mm2.
  • Keywords
    CMOS integrated circuits; automatic gain control; data communication equipment; decision feedback equalisers; feedforward; transceivers; 0.13 micron; 1.2 V; 290 mW; 30 dB; 4.9 to 6.4 Gbit/s; CMOS SerDes core; DFE; TXRX pair; decision-feedback equalization; feedforward equalization; receiver AGC; transmitter FFE; variable-gain amplifier; Bandwidth; CMOS technology; Clocks; Crosstalk; Decision feedback equalizers; Degradation; Reflection; Silicon; Switches; Tail;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493869
  • Filename
    1493869
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1668456