Title :
12Gb/s duobinary signaling with ×2 oversampled edge equalization
Author :
Yamaguchi, Kouichi ; Sunaga, Kazuhisa ; Kaeriyama, Shunichi ; Nedachi, Takaaki ; Takamiya, Makoto ; Nose, Kouichi ; Nakagawa, Yoshihiro ; Sugawara, Mitsutoshi ; Fukaishi, Muneo
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
A backplane transceiver in 90 nm CMOS that employs duobinary signaling over copper traces is described. To introduce duobinary signaling into data transfers on printed boards, three techniques are developed: 1) edge equalization for equalizer adaptation; 2) 2× oversampled transmitter equalizer for ISI control; and 3) 2b-transition-ensure encoding for clock recovery.
Keywords :
CMOS integrated circuits; adaptive equalisers; data communication equipment; intersymbol interference; partial response channels; synchronisation; transceivers; 12 Gbit/s; 90 nm; CMOS; Cu; ISI control; PCB data transfer; adaptive equalizer; backplane transceiver; clock recovery; copper trace duobinary signaling; oversampled transmitter equalizer; partial response signaling; transition-ensure encoding; two-times oversampled edge equalization; Bandwidth; Chromium; Circuits; Equalizers; Frequency; Intersymbol interference; National electric code; Transfer functions; Transmitters; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493873
