Implementation of a multi-bit /spl utri//spl Sigma/ A/DC without a correction RAM

This paper reports the SOI implementation of a multi-bit /spl utri//spl Sigma/ A/DC (Analog to Digital Converter) without using a correction RAM (Random Access Memory). By utilizing a shift register to store the data from a quantizer in parallel and then feedback serially into a one-bit D/AC (Digital to Analog Converter), multi-bit D/AC non-linearity can be eliminated. The reduction of the drain-to-body capacitor (C/sub db/), which is inherent to the SOI, greatly minimizes the power consumption of the fast clocking shift register. The design is implemented using a 2nd order, 4-bit, /spl utri//spl Sigma/ A/DC. The power to over clock the shift register is approximately 1.5% of the overall power. The analog front end (AFE) along with the two-path decimation filter was submitted for fabrication in the 150 /spl Aring/ Peregrine thin film SOS process in order to verify that the power dissipation is less than 1 mW. The projected the dynamic range of 108 dB at 2 KSPS.