Title :
A 10-bit 220-MSample/s CMOS sample-and-hold circuit
Author :
Waltari, Mikko ; Halonen, Kari
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland
Abstract :
A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in 0.5 μm CMOS technology. Measurements show 10 bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW at 3 V power dissipation
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; circuit feedback; sample and hold circuits; signal sampling; 0.5 micron; 10 bit; 25 mW; 3 V; ADC front-end; CMOS sample/hold circuit; double-sampling operation; fully differential S/H circuit; CMOS technology; Capacitors; Circuit topology; Clocks; Electronic circuits; Energy consumption; Feedback loop; Laboratories; Sampling methods; Voltage;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704345
