DocumentCode
1669210
Title
Metal gates for advanced sub-80-nm SOI CMOS technology
Author
Cheng, Binjie ; Maiti, B. ; Samavedam, S. ; Grant, J. ; Taylor, B. ; Tobin, P. ; Mogab, J.
Author_Institution
Digital DNA Labs., Motorola Inc., Austin, TX, USA
fYear
2001
Firstpage
91
Lastpage
92
Abstract
Extensive simulations were performed to evaluate the impact of the gate workfunction on the sub-80-nm PD and FD SOI device performance. The optimal gate workfunction for the 50 nm technology node is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS). Midgap gates are not suitable for PD SOI CMOS due to the severe short-channel effects, but are desirable for FD SOI CMOS.
Keywords
CMOS integrated circuits; integrated circuit modelling; silicon-on-insulator; work function; 50 nm; 80 nm; FD SOI CMOS; NMOS; PMOS; advanced sub-80-nm SOI CMOS technology; conduction band edge; gate workfunction; metal gates; midgap gates; optimal gate workfunction; short-channel effects; simulations; valence band edge; Boron; CMOS technology; Current measurement; Doping; Electrodes; Inorganic materials; Length measurement; MOS devices; Performance evaluation; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2001 IEEE International
Conference_Location
Durango, CO, USA
ISSN
1078-621X
Print_ISBN
0-7803-6739-1
Type
conf
DOI
10.1109/SOIC.2001.958000
Filename
958000
Link To Document