Title :
A 350MHz low-OSR ΔΣ current-steering DAC with active termination in 0.13 μm CMOS
Author :
Clara, Martin ; Klatzer, Wolfgang ; Wiesbauer, Andreas ; Straeussnigg, Dietmar
Author_Institution :
Infineon, Villach, Austria
Abstract :
A time-interleaved architecture overcomes the dynamic performance limitations of standard DWA switching. Clocked at 350MHz, the DAC with active output buffer achieves a linearity of 76dB for a signal swing of 1.536V and an effective resolution of 11.9b in a bandwidth of 29.16MHz. It is fabricated in a standard 0.13 μm CMOS process and consumes 62mW from a 1.5V supply.
Keywords :
CMOS integrated circuits; buffer circuits; delta-sigma modulation; ΔΣ current-steering DAC; 0.13 micron; 1.5 V; 29.16 MHz; 350 MHz; 62 mW; CMOS; active output buffer; active termination; low-OSR current-steering DAC; time-interleaved architecture; Capacitors; Clocks; Linearity; MOS devices; Operational amplifiers; Resistors; Signal generators; Switches; Switching frequency; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493897
