DocumentCode
1669261
Title
Integrated stereo delta-sigma class D amplifier
Author
Gaalaas, Eric ; Liu, Bill Yang ; Nishimura, Naoaki
Author_Institution
Analog Devices Inc., Wilmington, MA, USA
fYear
2005
Firstpage
120
Abstract
A 2×40W (into 4Ω with a 20V supply) integrated stereo ΔΣ class D amplifier with 100dB SNR is realized in a 0.6 μm CMOS process with DMOS transistors and buried Zener diodes. Feedback from power stage outputs gives 0.001% THD and 65dB PSRR. The modulator clock rate is 6MHz, but dynamically adjusted quantizer hysteresis reduces the output data rate to 450kHz, helping achieve 88% efficiency.
Keywords
CMOS integrated circuits; Zener diodes; audio-frequency amplifiers; delta-sigma modulation; feedback amplifiers; ΔΣ class D amplifier; 0.6 micron; 20 V; 4 ohm; 40 W; 450 kHz; 6 MHz; 88 percent; CMOS process; DMOS transistors; buried Zener diodes; delta-sigma class D amplifier; dynamically adjusted quantizer hysteresis; feedback; integrated stereo amplifier; modulator clock rate; Acoustic noise; Circuits; Clocks; Electromagnetic interference; Low-frequency noise; Power amplifiers; Power generation; Pulse amplifiers; Pulse width modulation; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1493898
Filename
1493898
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