• DocumentCode
    1669305
  • Title

    A 22GS/s 6b DAC with integrated digital ramp generator

  • Author

    Schvan, Peter ; Pollex, Daniel ; Bellingrath, Thomas

  • Author_Institution
    Nortel Networks, Ottawa, Ont., Canada
  • fYear
    2005
  • Firstpage
    122
  • Abstract
    A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3Vpp DNL<0.5LSB and INL<0.9LSB are measured. The highest glitch energy is 0.5pVs. Settling times are 70 and 40ps for full- and half-scale transitions, respectively.
  • Keywords
    BiCMOS integrated circuits; digital-analogue conversion; ramp generators; 1.2 W; 2 W; 3.3 V; 6 bit; DAC; digital ramp pattern generator; integrated digital ramp generator; Circuit simulation; Clocks; Counting circuits; Digital-analog conversion; Flip-flops; Network synthesis; Propagation delay; Signal design; Switches; Synchronous generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493899
  • Filename
    1493899
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1669305