A methodology for modeling embedded processors for architecture exploration

Architecture exploration for embedded systems is becoming an indispensable tool for System-on-Chip designers. This process requires the evaluation of many architectures that are generated during the exploration process. The evaluation process has a significant impact on the quality of the results and could consume a substantial amount of CPU time. Accordingly, the evaluation process should provide enough accuracy to guide the optimization process to promising points in the design space in reasonable time. In this paper an efficient approach for performance evaluation of embedded systems is proposed. Several cycle-accurate simulations are performed for commercial embedded processors used in our study. The simulation results are used to build Artificial Neural Network (ANN) models with accuracy up to 90% compared to cycle-accurate simulations with a very significant time saving.