Title :
An 81 MHz, 1280 × 720pixels × 30frames/s MPEG-4 video/audio CODEC processor
Author :
Yamauchi, Hiroyuki ; Okada, Shigeyuki ; Watanabe, Tsuyoshi ; Matsuo, Yoshihiro ; Suzuki, Thomas ; Ishii, Yasuo ; Mori, Tsugio ; Matsushita, Yoshifumi
Author_Institution :
Sanyo Electr. Co. Ltd., Gifu, Japan
Abstract :
A high-definition MPEG-4 CODEC processor capable of encoding 720p images (1280×720 pixels 30f/s) at 81MHz is presented. The CODEC is implemented with only 390k gates and an 80 kB SRAM. It is fabricated in a 0.13μm CMOS process on a 5.6mm×5.6mm die.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; multimedia communication; video codecs; 0.13 micron; 1280 pixel; 720 pixel; 81 MHz; 921600 pixel; CMOS process; SRAM; high-definition MPEG-4 CODEC processor; video/audio CODEC processor; Bandwidth; Codecs; Engines; High definition video; Image coding; MPEG 4 Standard; Motion estimation; Pixel; SDRAM; Video compression;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493903
