Title :
Layout optimization of cascode RF SOI transistors
Author :
Marenk, M. ; Ristolainen, E.
Author_Institution :
Tampere Univ. of Technol., Finland
Abstract :
Two different layouts of two MOSFETs connected in cascode were studied. The measured results were compared to simulations.
Keywords :
MOS integrated circuits; MOSFET; circuit optimisation; integrated circuit layout; silicon-on-insulator; MOSFETs; Si; cascode RF SOI transistors; interdigitized structure; layout optimization; simulations; Calibration; Circuit simulation; Fingers; Frequency measurement; Inductors; MOSFETs; Radio frequency; Scattering parameters; Silicon on insulator technology; VHF circuits;
Conference_Titel :
SOI Conference, 2001 IEEE International
Conference_Location :
Durango, CO, USA
Print_ISBN :
0-7803-6739-1
DOI :
10.1109/SOIC.2001.958008
