Title :
Circuit techniques for a 40Gb/s transmitter in 0.13μm CMOS
Author :
Kim, Jaeha ; Kim, Jeong-Kyoum ; Lee, Bong-Joon ; Hwang, Moon-Sang ; Lee, Hyung-Rok ; Lee, Sang-Hyun ; Kim, Namhoon ; Jeong, Deog-Kyoon ; Kim, Wonchan
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
Implemented in 0.13μm CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 231-1 PRBS transmitted eye has differential voltage swing of 549mVpp, rise time of 14ps, and clock jitter of 0.65rms and 4.9pp.
Keywords :
CMOS integrated circuits; circuit feedback; flip-flops; radio transmitters; timing circuits; 0.13 micron; 38.4 Gbit/s; 40 Gbit/s; CMOS; PRBS transmitted eye; bandwidth enhancement; circuit techniques; negative feedback; pulsed latch-based dividers; retimers; shunt-and-double-series inductive peaking; timing closure; transmitter; Bandwidth; CMOS process; Circuits; Clocks; Delay; Geometry; Inductors; Parasitic capacitance; Shunt (electrical); Transmitters;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493913
