Title :
Processor Grain Size and Overhead for Massive Parallelism
Author_Institution :
School of Electrical Engineering, Georgia Institute of Technology
fDate :
10/19/1992 12:00:00 AM
Keywords :
Algorithm design and analysis; Delay; Grain size; Magnetic heads; Parallel architectures; Pareto analysis; Power system management; Process design; Specification languages; Throughput;
Conference_Titel :
Massively Parallel Processing., The New Frontiers. A Workshop on Future Directions of
Print_ISBN :
0-8186-4410-9
DOI :
10.1109/FDMPP.1992.588637
