Modeling the gated-diode response of an irradiated SOI back-channel interface

Author

Lawrence, R.K. ; Salman, A.A. ; Ioannou, D.E. ; Jenkins, W.C. ; Liu, S.T.

Author_Institution

SFA Inc., Largo, MD, USA

fYear

2001

Firstpage

127

Lastpage

128

Abstract

In this work the gated-diode technique has been applied to n-channel SOI MOSFETs that were part of a test vehicle used for a 0.25 /spl mu/m SOI CMOS product development. We have shown that the gated-diode technique is a powerful technique for the evaluation of the Si-film/buried-oxide interface, and that the technique is simple in measurement configuration. Our 2D numerical simulation of the SOI back-channel gated-diode results indicates that the back-channel radiation-induced interface state concentration can be modeled as an acceptor interface state at an energy of 0.7eV.

Keywords

CMOS integrated circuits; MOSFET; buried layers; impurity states; interface states; semiconductor device models; silicon-on-insulator; 2D numerical simulation; SOI CMOS product development; Si; Si-film/buried-oxide interface; acceptor interface state; back-channel radiation-induced interface state; gated-diode response; irradiated SOI back-channel interface; measurement configuration; modeling; n-channel SOI MOSFETs; CMOS technology; Current measurement; Density measurement; Diodes; Interface states; Laboratories; MOSFET circuits; Numerical simulation; Particle measurements; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2001 IEEE International

Conference_Location

Durango, CO, USA

ISSN

1078-621X

Print_ISBN

0-7803-6739-1

Type

conf

DOI

10.1109/SOIC.2001.958019

Filename

958019