Title :
A 1V 24GHz 17.5mW PLL in 0.18μm CMOS
Author :
Ng, Alan W L ; Leung, Gerry C T ; Kwok, Ka-Chun ; Leung, Lincoln L K ; Luong, Howard C.
Author_Institution :
Hong Kong Univ. of Sci. & Technol., China
Abstract :
A 1V 24GHz fully integrated PLL is designed in a 0.18μm. CMOS process using a transformer-feedback VCO and a stacked frequency divider. The PLL measures an in-band phase noise of -106.3dBc/Hz at 100kHz offset and an out-of-band phase noise of -119.1dBc/Hz at 10MHz offset. It consumes 17.5mW from a 1V supply and occupying an area of 0.55mm2.
Keywords :
CMOS integrated circuits; circuit feedback; frequency dividers; phase locked loops; phase noise; transformers; voltage-controlled oscillators; 0.18 micron; 1 V; 17.5 mW; 24 GHz; CMOS; fully integrated PLL; phase noise; stacked frequency divider; transformer-feedback VCO; Circuits; Energy consumption; Feedback; Filters; Frequency conversion; Low voltage; Partial discharges; Phase locked loops; Phase noise; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493917
