• DocumentCode
    1669795
  • Title

    Structural heuristics for SAT-based ATPG

  • Author

    Tille, Daniel ; Eggersglüss, Stephan ; Le, Hoang M. ; Drechsler, Rolf

  • Author_Institution
    Inst. for Comput. Sci., Univ. of Bremen, Bremen, Germany
  • fYear
    2009
  • Firstpage
    77
  • Lastpage
    82
  • Abstract
    Due to ever increasing design sizes more efficient tools for Automatics Test Pattern Generation (ATPG) are needed. The application of the Boolean satisfiability problem (SAT) to ATPG has been shown to be a robust alternative to traditional ATPG techniques. A major challenge of research in the field of SAT-based ATPG is to obtain a robust algorithm which can solve hard SAT instances reliably without slowing down easy-to-solve SAT instances. This is particular important, since easy-to-solve SAT instances form the majority of an ATPG run. This paper proposes two structural heuristics. The first one uses testability measurements to obtain an improved initial variable order while the second heuristic prunes many easy-to-test faults by finding easy-to-control paths. Experimental results on large industrial designs confirm that the proposed methodologies result in a significant overall speed-up.
  • Keywords
    automatic test pattern generation; computability; Boolean satisfiability problem; SAT-based ATPG; automatic test pattern generation; design sizes; easy-to-control paths; easy-to-solve SAT instances; easy-to-test faults; hard SAT instances; large industrial designs; structural heuristics; testability measurements; Automatic test pattern generation; Circuit faults; Controllability; Integrated circuit modeling; Logic gates; Robustness; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on
  • Conference_Location
    Florianopolis
  • Print_ISBN
    978-1-4577-0237-2
  • Type

    conf

  • DOI
    10.1109/VLSISOC.2009.6041334
  • Filename
    6041334