Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΔΣ modulator with level shifter

Author

Kokubo, Masaru ; Kawamoto, Takashi ; Oshima, Takashi ; Noto, Takayuki ; Suzuki, Masato ; Suzuki, Shigeyuki ; Hayasaka, Takashi ; Takahashi, Tomoaki ; Kasai, Jun

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

2005

Firstpage

160

Abstract

Implemented in a 0.15μm CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a ΔΣ modulator An adaptive level shifter is adopted for expanding the input range of the ΔΣ modulator. The 1.5GHz prototype achieves the peak spurious reduction level of 20.3dB and the random jitter of 8.1 ps in a 250-cycle averaging period.

Keywords

CMOS integrated circuits; clocks; delta-sigma modulation; jitter; peripheral interfaces; phase locked loops; ΔΣ modulator control; 0.15 micron; 1.5 GHz; CMOS process; adaptive level shifter; fractional PLL; peak spurious reduction; random jitter; serial ATA; spread-spectrum clock generator; Clocks; Counting circuits; Delta modulation; Electromagnetic interference; Frequency; Jitter; Phase locked loops; Phase modulation; Spread spectrum communication; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493918

Filename

1493918

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1669806