DocumentCode :
1669941
Title :
Congestion driven placement for Mesh-based FPGA architecture with local interconnect
Author :
Marrakchi, Z. ; Turki, M. ; Rebourg, J. ; Abid, Mohamed ; Mehrez, H.
Author_Institution :
FlexRAS Technol., Paris, France
fYear :
2011
Firstpage :
1
Lastpage :
5
Abstract :
In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently the device total area by 10% in average. In terms of circuit performance, we notice that congestion alleviation allows timing-driven router to reduce critical path delays despite wirelength increasing. This is due essentially to timing closure improvement.
Keywords :
field programmable gate arrays; network routing; congestion driven placement technique; critical path delays reduction; field programmable gate arrays; local interconnect connections; mesh-based FPGA architecture; signal avoidance; timing closure improvement; timing-driven router; white spaces; Computer architecture; Cost function; Delay; Field programmable gate arrays; Integrated circuit interconnections; Routing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics (ICM), 2011 International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4577-2207-3
Type :
conf
DOI :
10.1109/ICM.2011.6177368
Filename :
6177368
Link To Document :
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