DocumentCode
1669980
Title
Design, implementation and analysis of fully digital 1-D controllable multiscroll chaos
Author
Mansingka, A.S. ; Radwan, A.G. ; Salama, K.N.
Author_Institution
Electr. Eng. Program, King Abdullah Univ. of Sci. & Technol. (KAUST), Thuwal, Saudi Arabia
fYear
2011
Firstpage
1
Lastpage
5
Abstract
This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital design is exploited to provide real-time controllability of (i) number of scrolls, (ii) position in 1-D space, (iii) Euler step size and (iv) system parameter. The effect of variations in these fields on the maximum Lyapunov exponent (MLE) is analyzed. The system is implemented using Verilog HDL and synthesized on an Xilinx Virtex 4 FPGA, exhibiting area utilization less than 3.5% and high performance with experimentally verified throughput up to 3.33 Gbits/s. This fully digital system enables applications in modulation schemes and chaos-based cryptosystems without analog to digital conversion.
Keywords
chaos generators; cryptography; field programmable gate arrays; hardware description languages; modulation; 3rd-order jerk system; Euler approximation; Euler step size; MLE; Verilog HDL; Xilinx Virtex 4 FPGA; chaos generator analysis; chaos generator design; chaos-based cryptosystems; digital design; fully-digital 1D controllable multiscroll chaos generator; maximum Lyapunov exponent; modulation schemes; real-time controllability; scroll number; staircase nonlinearity; system parameter; Approximation methods; Chaotic communication; Field programmable gate arrays; Generators; Hardware design languages; Maximum likelihood estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (ICM), 2011 International Conference on
Conference_Location
Hammamet
Print_ISBN
978-1-4577-2207-3
Type
conf
DOI
10.1109/ICM.2011.6177371
Filename
6177371
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