Title :
An 80MHz 4× oversampled cascaded ΔΣ-pipelined ADC with 75dB DR and 87dB SFDR
Author :
Bosi, Alessandro ; Panigada, Andrea ; Cesura, Giovanni ; Castello, Rinaldo
Author_Institution :
STMicroelectronics, Pavia, Italy
Abstract :
A 2nd-order 4b ΔΣ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18μm CMOS chip consumes 240mW including reference generator, digital decimator and correction logic.
Keywords :
CMOS logic circuits; analogue-digital conversion; delta-sigma modulation; integrated circuit noise; linearisation techniques; pipeline processing; signal sampling; ΔΣ modulator; 0.18 micron; 10 MHz; 240 mW; 80 MHz; CMOS chip; SFDR; background digital linearization; cascaded ΔΣ-pipelined ADC; correction logic; digital decimator; noise-cancellation algorithms; oversampled ΔΣ-pipelined ADC; reference generator; Bandwidth; Dynamic range; Finite impulse response filter; Frequency; Modems; Noise cancellation; Noise shaping; Pipelines; Quantization; Transfer functions;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493925
