Title :
Design and performance evaluation of on chip network with Transaction Level Modeling
Author :
Abid, Nourddine ; Chouchene, Wissem ; Attia, Brahim ; Zitouni, Abdelrim ; Tourki, Rached
Author_Institution :
Electron. & Micro-Electron. Lab., Monastir Univ., Monastir, Tunisia
Abstract :
Networks-On-Chip (NoC) are appropriate solutions to connect the increasing number of components being integrated into Systems-on-Chip. To simulate such systems at early design stage, abstraction techniques like Transaction Level Modeling (TLM) are used to describe the communication. In this paper, three different mesh 2D sizes are evaluated using SystemC TLM2 with a single transaction and reduced accuracy. Register Transfer Level (RTL) model and Loosely Timed (LT) Transaction Level models are compared.
Keywords :
network synthesis; network-on-chip; performance evaluation; transaction processing; LT transaction level model; NoC; RTL model; SystemC TLM2 evaluation; abstraction technique; loosely timed transaction level model; mesh 2D size; network-on-chip; performance evaluation; register transfer level model; system-on-chip; transaction level modeling; IP networks; Mesh networks; Routing; Sockets; Throughput; Time domain analysis; Time varying systems; Network on Chip; TLM router; Traffic pattern; Transaction Level Modeling;
Conference_Titel :
Microelectronics (ICM), 2011 International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4577-2207-3
DOI :
10.1109/ICM.2011.6177373
